|1||VBAT, connect to VDD if not used|
|3||OSC32_IN (LSE/RTC), leave unconnected when not used|
|4||OSC32_OUT (LSE/RTC), leave unconnected when not used|
|7||NRST (Reset), not 5V tolerant, connect 10k resistor to VDD when not used|
|14||Wakeup or EFC (PA0), internal pulldown|
|20||Data Ready (PA4), high active output|
|22||SPI MISO or UART Busy (PA6)|
|23||SPI MOSI (PA7), internal pulldown|
|24||SD WP (PC4), high=write protected, internal pullup|
|25||SD CD (PC5), high=no card, internal pullup|
|28||BOOT1, connect 10k resistor to GND|
|31||VCAP_1, connect 2.2uF capacitor to GND|
|35||USB U1 D- (PB14), 22 ohm resistor in series|
|36||USB U1 D+ (PB15), 22 ohm resistor in series|
|39||SD D0 (PC8), internal pullup|
|40||SD D1 (PC9), internal pullup|
|42||UART TX (PA9)|
|43||UART RX or SPI/I2C Busy (PA10)|
|44||USB U0 D- (PA11), 22 ohm resistor in series|
|45||USB U0 D+ (PA12), 22 ohm resistor in series|
|46||SWDIO (SWD), leave unconnected|
|47||VCAP_2, connect 2.2uF capacitor to GND|
|49||SWCLK (SWD), leave unconnected|
|50||SPI CS (PA15), internal pulldown|
|51||SD D2 (PC10), internal pullup|
|52||SD D3 (PC11), internal pullup|
|53||SD CLK (PC12)|
|54||SD CMD (PD2), internal pullup|
|55||SPI SCK (PB3), internal pullup|
|58||I2C SCL (PB6)|
|59||I2C SDA (PB7)|
|60||BOOT0, connect 10k resistor to GND or VDD|
Do not connect any pin that has no function (description -).
A standard 3.3V power source (with at least 50mA) for digital circuits is needed to power the FATSC processor. 100nF decoupling capacitors are needed near every VDD power pin. If the power supply regulator is not nearby then add a 4.7 to 22uF capacitor near to the FATSC processor.
The main system clock is provided with a 12MHz HSE crystal (load capacitance about 18pF). For the optional RTC a 32.768kHz LSE crystal (load capacitance about 12pF) is needed. There is a failover to the internal clock, if the external HSE crystal fails. The crystal operating states are shown in the auxiliary status register.
The internal clock resets on power loss. With an external 32.768kHz crystal and backup battery on VBAT (1.7-3.6V) the clock can run independently. To prevent power loss on the VBAT power input two diodes can be used to combine the battery source and the main power (VDD). See the FATSC Dev-Kit schematics for further information.
On the USB host ports a 4.7 to 22uF capacitor and a polyfuse for over-current protection is recommended. The USB data signals have to be connected with 22 ohm resistors to the FATSC processor. For ESD and EMI protection recommendations have a look in the STM32 Appnote AN4879.
A 4.7 to 22uF capacitor is recommended on the SD socket power supply pin and 47k to 100k pullup resistors on the D0, D1, D2, D3 and CMD pin. On a card insertion a high current can be drawn and the power circuit has to be able to deliver this surge current. Best practice is to use a separate 3.3V voltage regulator (with at least 100mA) for the SD card to prevent voltage drops on the 3.3V power supply of the FATSC processor.
With the SWD pins an in-system-programming of an empty STM32F205 controller during production is possible. We can provide a special programming adapter for this. Please ontact us by mail for further information.